Demand for ever decreasing chip fabrication costs forces the industry to develop new solutions for inexpensive and reliable chip testing devices. A common component for repetitively contacting contact arrays of tested circuit chips is an interconnect assembly that is placed adjacent a test apparatus contact array that has contact pitch corresponding to the tested chips' carrier (package) contact pitch. During packaged chip testing, a package is brought with its contact array into contact with the interconnect assembly such that an independent conductive contact is established between each of the package's contacts and the corresponding contact of the test apparatus.
Interconnect arrays have to provide highly uniform contact resistance over a desirably large deflection range to reduce degrading measurement influences of dimensional test contact variations. With decreasing contact pitches and increasing numbers of test contacts of packaged chips, it becomes increasingly challenging to design interconnect arrays that can be fabricated with low fabrication costs while meeting the demand for maximum deflection with an ever decreasing footprint available for each interconnect stage. The present invention meets this challenge.
Further desirable characteristics of an interconnect array are minimum path lengths and complexity of the individual conductive paths within the interconnect array to improve electrical performance and minimal overall contact force necessary to reliably establish all required conductive paths across the interconnect array. These characteristics become increasingly important as test frequencies and number of conductive paths within a single interconnect array increase. The present invention addresses these needs.
Each individual interconnect has to provide a maximum deflection within a given footprint commonly defined by the contact pitch. At the same time, each interconnect has to provide sufficient structural stiffness to warrant sufficient scribing in the interface between contact tips of the interconnects and the respective contacts of the package's contacts. In the prior art, planar arrayed interconnects have been fabricated with varying shapes, commonly embedded in substantially rigid dielectric carrier structures or carrier frames. For example, interconnects have been fabricated as see-saw structures integrated with torsion beams or torsion bridges that assist in increasing the interconnects' overall deflection. The interconnects are embedded thereby in the carrier structure such that the carrier structure remains structurally substantially unaffected by the interconnects deflections. Spring loaded deflection and wear resistant contacting features are provided by the same monolithic structure. This poses a significant limitation on maximizing deflection range due to the opposing material requirements for stiffness of the contacting features and resilience of the spring features. In the present invention addresses this problem.
For a cost effective and reliable fabrication of interconnect assemblies there exists a need for a interconnect configuration that requires a minimum number of involved fabrication steps and individual components. Fabrication steps are preferably performed along a single axis. Assembling operations are preferably avoided. The present invention addresses this need.